Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computers consume approximately 13% of the entire electricity supply for the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. And as servers, desktop computers, notebooks, ultra-books, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology), the effect of computing device sales stretches well outside the realm of energy consumption into a substantial, direct effect on The United States economy, as computing device related sales already have a large causal relationship with The United States Gross Domestic Product. Though specific statistics relevant to the United States of America have been presented here, the need for enhancing energy efficiencies and reducing energy or power consumption are applicable throughout the world.
For example, a computer system may comprise a processor, which may include a core area and an uncore area. The core area may include one or more processing cores, caches (L1 and L2, for example), line-fill buffers and the uncore area may comprise last level caches, a memory controller, and such other blocks. The processor power management techniques aim at reducing the power consumed by the core area by changing the power state (such as C0, C1, C2, C3, C4, C6) of the cores within the processor based on some criteria such as activity time or sleep time of the processor.
However, deeper power saving states (C-states) such as C6 may be associated with a high energy cost for the transitions and such costs may become more significant as residency times of C-states shrink due to high interrupt rates of real-time needs or due to the high interrupt rates caused by I/O traffic. Incorrect C-state usage will result in battery life loss instead of gain. Furthermore, incorrect selection of the power saving state may increase the interrupt response time, which may affect the performance. The selection of a power saving state (or C-state) is therefore a balance between the energy savings associated with the power state and the performance loss due to the exit latency. Also, entering a deeper sleep state may not be energy conserving (or cost saving) activity if the residency time in that deeper sleep state is not long enough to justify the entry into the deeper sleep state. Such an attempt to enter into the deeper sleep state may be therefore inefficient. The current approaches such as ACPI does not have a notion of energy cost of a C-states election and current operating systems (OS) choose C-states based on average active time residency or expected sleep duration and the state exit latency.